An FPGA Nasdaq ITCH 5.0 parser

An FPGA Nasdaq ITCH 5.0 parser

· 1 min read

⚠️This article is in the works, and will soon be completed.


I’ve recently been exploring the area of High Frequency Trading (HFT) and have written an ITCH parser in C++ and SystemVerilog. While my implementation in both seems to work, there’s a lot that can be improved (which is where the real learning happens). This article is an exploration of the writing the ITCH 5.0 parser as well as a brand new implementation in Rust!

Please note, this article is currently being written up, and may not be finished at the time of reading.

Initial exploration

To get acquainted with the ITCH protocol, I started with an implementation of an order book engine in Python. This was pretty simple, and I’ll walk through the implementation soon.